The present invention relates to receiver circuits, and in particular to clocked receivers for amplifying low-swing signals to full-rail CMOS.
Faster VLSI devices put an ever increasing demand on bandwidth requirements for point-to-point and distributed busses. Frequently these busses experience large overshoots and undershoots if an attempt is made to drive them to the full range of the power supply. One effective technique used to make these interfaces run faster without such noise problems is to reduce the voltage swings below the full supply rails. This creates a new requirement for fast, low-swing data receivers and output drivers.
The requirement that a data receiver must be fast implies that it must have high bandwidth internally. Since signals inside CMOS VLSI devices are typically distributed as full-swing signals for noise-immunity and ease of use, the receiver should also have gain to amplify from low-swing to full-swing.
However, VLSI amplifiers in general experience a limited gain-bandwidth product. Thus, if it is desired to amplify low swings to full-rail CMOS (gain), some speed (bandwidth) is usually lost. In order to overcome speed and bandwidth limitations, two or more gain stages are often put in series. This unfortunately results in higher latency to valid output data. Achieving low latency is very important because it effects the actual time required to get the first data off of a bus and into the device. Another desirable quality for a low-swing receiver is a large input common-mode voltage range. Frequently, the actual input voltage levels are determined by many other factors in the environment, such as output driver characteristics, line impedance, available power supplies, etc. An input receiver with a large common mode range can avoid further constraining the voltage range. In summary, basic desirable qualities for a low-swing receiver include 1) good gain, 2) low latency, and 3) large common mode range. As with many VLSI circuits, additional favorable qualities include small physical area and low power consumption.
Receivers in the prior art, such as that of U.S. Pat. No. 5,319,755, entitled "High Speed Bus System", by Horowitz & Lee, as illustrated in FIG. 1 have several undesirable characteristics which are avoided in this invention.
First, in Horowitz/Lee, the input differential data BusData and Vref are sampled by a full-CMOS passgate, which means that the P+ diffusion of the PFETs of T1 and T2 are connected directly to device pins. This can lead to a latch-up condition if the power-up sequence is not tightly controlled, i.e., the pin is powered up before the well.
Second, the circuit is dependent on the distribution of a bias voltage, labelled VBIAS. U.S. Pat. No. 5,023,488 of Gunning has a similar bias requirement. In general, input receivers are usually distributed across the full width of a VLSI device. Voltage bias lines running large distances across a mixed-signal CMOS device are frequently disturbed by coupling capacitances to adjacent high-speed wires or by the substrate itself. It can in practice be very difficult to distribute quiet voltage-bias wires in a noisy environment.
Third, the circuit makes use of the signals CLK and nCLK, with each going into complementary devices. If the skew between the rising edge of CLK and the falling edge of nCLK is not very well controlled, it can lead to a condition where the data feeds through from the master to the slave latch a phase earlier than desired. Lastly, the latency of this design is quite high, requiring at least one full clock cycle plus the clock-to-Q delay of the final sense-amplifier.